thumbs up for this project (everything RISC-V is usually).
I write rv64 assembly (nearly core only, without memory reservation instructions) and run it on x86_64 with a very small (x86_64 assembly written) interpreter.
And your are right, I have had thoughts about a "RISC-V" x86_64 compiler (but it will probably require some runtime unfortunately).
Hopefully, rv22+ hardware with ultra-performant µ-architecture and with the latest silicon process will happen sooner than we expect. One less PI toxic lock and cleaner, _really standard_ assembly (the end game of much software).
thumbs up for this project (everything RISC-V is usually).
I write rv64 assembly (nearly core only, without memory reservation instructions) and run it on x86_64 with a very small (x86_64 assembly written) interpreter.
And your are right, I have had thoughts about a "RISC-V" x86_64 compiler (but it will probably require some runtime unfortunately).
Hopefully, rv22+ hardware with ultra-performant µ-architecture and with the latest silicon process will happen sooner than we expect. One less PI toxic lock and cleaner, _really standard_ assembly (the end game of much software).