He designs a stack-based ISA with ten instructions.
I've previously written [1] about reducing RISC-V RV32I down to 10 instructions `addi`, `add`, `nand`, `sll`, `sra`, `jal`, `jalr`, `blt`, `lw`, `sw` [2]. Except for subword stores the missing instructions can be emulated with at most 4 instructions.
I implemented the `countPrimes` function in my own benchmark [3] using just this subset [4] and found a 28% code size expansion but only a 3% speed penalty.
He designs a stack-based ISA with ten instructions.
I've previously written [1] about reducing RISC-V RV32I down to 10 instructions `addi`, `add`, `nand`, `sll`, `sra`, `jal`, `jalr`, `blt`, `lw`, `sw` [2]. Except for subword stores the missing instructions can be emulated with at most 4 instructions.
I implemented the `countPrimes` function in my own benchmark [3] using just this subset [4] and found a 28% code size expansion but only a 3% speed penalty.
[1] https://new.reddit.com/r/RISCV/comments/w0iufg/how_much_coul...
[2] or 11 if you keep a strict subset by including `and` and `xor` instead of `nand`
[3] https://hoult.org/primes.txt
[4] https://hoult.org/primes.S